1. Field of the Invention
The invention relates to the field of cleaning associated with metal interlayer connections, particularly plugs used in integrated circuits.
2. Prior Art
Integrated circuits have long used layers of metals for the upper levels of circuitry. These metal layers generally have interlayer connections (interconnects) and sometimes interconnects that allow direct connections to the lower levels of circuitry defined in the silicon substrate or polysilicon levels. Subsequent complexity has added more layers of metalization separated by dielectric layers, and has shrunk the size of the interlayer connections. These interlayer connections are often made with materials different from the primary metal of each layer. The openings in the dielectric layers are typically called contacts or vias, and the fill material is sometimes called a plug. These fill or plug materials are selected for their superior deposition properties in small geometries, in addition to their conductivity. As the physical dimensions of these interlayer connections have shrunk the reliability problems associated with electromigration have increased.
In typical processing for forming an interlayer connection, first an opening is patterned and etched through an interlayer dielectric. The dielectric may be doped glass such as boron-phosphorous glass (BPSG), spun glasses, or deposited or thermally grown oxides commonly referred to as an interlayer dielectric (ILD).
In some processes a thin adhesion layer is next required in preparation for the material used to fill the via or contact. A typical material is titanium nitride (TiN) which may be deposited by physical sputtering or a chemical vapor deposition (CVD) process. This adhesion layer covers the wafer surface and to various degrees the bottom and sidewalls of the contact or via.
The next step is the deposition of the interlayer connection (interconnect) material, which completely fills the openings as well as covering the surface of the dielectric layer or adhesion layer. A typical process deposits tungsten. This material is then partially removed by plasma etching or mechanical polishing until the surface film is removed and the remaining tungsten is somewhat coplanar with the opening in the dielectric. In this manner the interconnect between the layers of circuitry is defined and the wafer is ready for the next layer.
It is necessary to remove substantially all of the interconnect fill material from the surface of the dielectric prior to deposition of the next metal layer. For example, if tungsten is used as an interconnect material, any tungsten residue may create an electrical defect between the metal circuit lines of the overlying layer.
Moreover, the surface of the dielectric layer must typically be cleaned of residues remaining from the etch back or polish process again to prevent pattern disruption in the next metal circuit layer.
Finally, the surface of the interconnect filled via must be prepared for forming a low resistance interface for connection to the next metal layer. This is frequently done in the metal deposition machine using such techniques as argon sputtering. However, this process creates problems of its own as particles from the sputtering apparatus become deposited on the wafer, again creating pattern defects.
In typically processing in preparation for metal deposition of the filled interconnects, combinations of solvents and acids are used to clean the residues and prepare an interface for good conduction. However, this processing typically results in the formation of voids in the metal-interconnect interface as shown in FIG. 5. Additionally, sharp features of the interconnect material can create electric field nonuniformities that are undesirable.
The present invention provides a novel cleaning step for the interlayer connections that addresses these issues and, in fact, can be used to reduce the argon sputtering requirements.